Packages the other modules into a `Project` class which simplifies interfacing with any connected FPGAs and scripting, reading/writing to memory, controlling locations, etc.

class Project[source]

Project(projname, projdir='./', chip=DE10 Nano 5CSEBA6U23I7 from X=1 to X=88, Y=1 to Y=80 MLAB X-coords: [3, 6, 8, 15, 21, 25, 28, 34, 39, 47, 52, 59, 65, 72, 78, 82, 84, 87] M10K X-coords: [5, 14, 26, 38, 41, 44, 49, 58, 69, 76, 89] DSP X-coords: [20, 32, 54, 86] LAB X-coords: else, templatefile=None, **kwargs)

p=Project(projname='WCD',projdir=r'C:\Users\Noeloikeau Charlot\Desktop\Research\WCD\Quartus')

p.hw

['DE-SoC [USB-1]', 'DE-SoC [USB-2]']
p.dev

['@2: 5CSEBA6(.|ES)/5CSEMA6/.. (0x02D020DD)',
 '@2: 5CSEBA6(.|ES)/5CSEMA6/.. (0x02D020DD)']
p.program_all()

p.get_insts()

{'DE-SoC [USB-1]': [['0', '1', '1', 'RW', 'ROM/RAM', 'BIT'],
  ['1', '1', '3', 'RW', 'ROM/RAM', 'MULT'],
  ['2', '1', '2', 'RW', 'ROM/RAM', 'MULT'],
  ['3', '512', '1300', 'RW', 'ROM/RAM', 'READ'],
  ['4', '512', '1300', 'RW', 'ROM/RAM', 'READ'],
  ['5', '512', '1300', 'RW', 'ROM/RAM', 'READ'],
  ['6', '512', '1300', 'RW', 'ROM/RAM', 'READ']],
 'DE-SoC [USB-2]': [['0', '1', '1', 'RW', 'ROM/RAM', 'BIT'],
  ['1', '1', '3', 'RW', 'ROM/RAM', 'MULT'],
  ['2', '1', '2', 'RW', 'ROM/RAM', 'MULT'],
  ['3', '512', '1300', 'RW', 'ROM/RAM', 'READ'],
  ['4', '512', '1300', 'RW', 'ROM/RAM', 'READ'],
  ['5', '512', '1300', 'RW', 'ROM/RAM', 'READ'],
  ['6', '512', '1300', 'RW', 'ROM/RAM', 'READ']]}
p.read(inst=0)

array([0])
p.read_all(inst=0)

array([[1],
       [1]])
p.read_write([(0,'w',1),(0,'r')])

array([1])
p.read_write_all([(0,'w',1),(0,'r')])

array([[1],
       [1]])
p.read_write([(1,'w',3,3),(1,'r')])

array([0, 1, 1])
p.read_write_all([(1,'w',3,3),(1,'r')])

array([[0, 1, 1],
       [0, 1, 1]])
p.read(inst=6).shape

(512, 1300)